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March 2007
HYS64T128020EDL-[25F/2.5/3/3S/3.7]-C HYS64T256020EDL-[25F/2.5/3/3S/3.7]-C
2 0 0 - P i n S O - D I M M D D R 2 S D R A M Mo d u l e s DDR2 SDRAM SO-DIMM SDRAM RoHS Compliant
Internet Data Sheet
Rev. 1.0
Internet Data Sheet
HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
HYS64T128020EDL-[25F/2.5/3/3S/3.7]-C, HYS64T256020EDL-[25F/2.5/3/3S/3.7]-C
Revision History: 2007-03, Rev. 1.0 Page All 32, 33 52, 53 All Subjects (major changes since last revision) Adapted internet edition Added IDD values. Pakage Outline drawings updated with SPD/TS/ Combidevice Footnote. Initial document
Previous Revision: 2006-11, Rev. 0.5
We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc@qimonda.com
qag_techdoc_rev400 / 3.2 QAG / 2006-08-07 11212006-D34H-5W6Z
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Internet Data Sheet
HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
1
Overview
This chapter gives an overview of the 200-Pin SO-DIMM DDR2 SDRAM Modules product family and describes its main characteristics.
1.1
Features
* * * * * * * * * * Auto Refresh for temperatures above 85 C tREFI = 3.9 s. Programmable self refresh rate via EMRS2 setting. Programmable partial array refresh via EMRS2 settings. DCC enabling via EMRS2 setting. All inputs and outputs SSTL_1.8 compatible Off-Chip Driver Impedance Adjustment (OCD) and On-Die Termination (ODT) Serial Presence Detect with E2PROM SO-DIMM Dimensions (nominal): 30 mm high, 67.6 mm wide Based on standard reference layouts Raw Card "A" and "F" RoHS compliant products1)
* 200-Pin PC2-6400, PC2-5300 and PC2-4200 DDR2 SDRAM memory modules. * 128M x 64, 256M x 64 module organization and 64M x 16 and 128M x 8 chip organization * Standard Double-Data-Rate-Two Synchronous DRAMs (DDR2 SDRAM) with a single + 1.8 V ( 0.1 V) power supply * 1 GB and 2 GB modules built with 1-Gbit DDR2 SDRAMs in PG-TFBGA-84 and PG-TFBGA-60 chipsize packages * All speed grades faster than DDR2-400 comply with DDR2-400 timing specifications. * Programmable CAS Latencies (3, 4,5 and 6 ), Burst Length (8 & 4) and Burst Type * Auto Refresh (CBR) and Self Refresh
TABLE 1
Performance Table
Product Type Speed Code Speed Grade Max. Clock Frequency @CL6 @CL5 @CL4 @CL3 Min. RAS-CAS-Delay Min. Row Precharge Time Min. Row Active Time Min. Row Cycle Time -2.5F PC2-6400 5-5-5 -2.5 PC2-6400 6-6-6 400 333 266 200 15 15 45 60 -3 PC2-5300 4-4-4 -- 333 333 200 12 12 45 57 -3S PC2-5300 5-5-5 -- 333 266 200 15 15 45 60 -3.7 PC2-4200 4-4-4 -- 266 266 200 15 15 45 60 Unit -- MHz MHz MHz MHz ns ns ns ns
fCK6 fCK5 fCK4 fCK3 tRCD tRP tRAS tRC
400 400 266 200 12.5 12.5 45 57.5
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
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Internet Data Sheet
HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
1.2
Description
The memory array is designed with 1-Gbit Double-Data-RateTwo (DDR2) Synchronous DRAMs. Decoupling capacitors are mounted on the PCB board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and are write protected; the second 128 bytes are available to the customer.
The Qimonda HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C module family are small outline DIMM modules "SO-DIMMs" with 30 mm height based on DDR2 technology. DIMMs are available as non-ECC modules in 128M x 64 (1GB) and 256M x 64 (2 GB) organization and density, intended for mounting into 200-pin connector sockets.
TABLE 2
Ordering Information for RoHS Compliant Products
Product Type1) PC2-6400 HYS64T128020EDL-25F-C HYS64T256020EDL-25F-C PC2-6400 HYS64T128020EDL-2.5-C HYS64T256020EDL-2.5-C PC2-5300 HYS64T128020EDL-3-C HYS64T256020EDL-3-C PC2-5300 HYS64T128020EDL-3S-C HYS64T256020EDL-3S-C PC2-4200 HYS64T128020EDL-3.7-C HYS64T256020EDL-3.7-C 1 GB 2Rx16 PC2-4200S-444-12-A0 2 GB 2Rx8 PC2-4200S-444-12-F0 2 Rank, Non-ECC 2 Rank, Non-ECC 1 Gbit (x16) 1 Gbit (x8) 1 GB 2Rx16 PC2-5300S-555-12-A0 2 GB 2Rx8 PC2-5300S-555-12-F0 2 Rank, Non-ECC 2 Rank, Non-ECC 1 Gbit (x16) 1 Gbit (x8) 1 GB 2Rx16 PC2-5300S-444-12-A0 2 GB 2Rx8 PC2-5300S-444-12-F0 2 Rank, Non-ECC 2 Rank, Non-ECC 1 Gbit (x16) 1 Gbit (x8) 1 GB 2Rx16 PC2-6400S-666-12-A0 2 GB 2Rx8 PC2-6400S-666-12-F0 2 Rank, Non-ECC 2 Rank, Non-ECC 1 Gbit (x16) 1 Gbit (x8) 1 GB 2Rx16 PC2-6400S-555-12-A0 2 GB 2Rx8 PC2-6400S-555-12-F0 2 Rank, Non-ECC 2 Rank, Non-ECC 1 Gbit (x16) 1 Gbit (x8) Compliance Code2) Description SDRAM Technology
1) All Product Type numbers end with a place code, designating the silicon die revision. Example: HYS64T128020EDL-3.7-C, indicating Rev. "C" dies are used for DDR2 SDRAM components. For all Qimonda DDR2 module and component nomenclature see Chapter 6 of this data sheet. 2) The Compliance Code is printed on the module label and describes the speed grade, for example "PC2-4200S-444-12-A0", where 4200S means Unbuffered SO-DIMM modules with 4.26 GB/sec Module Bandwidth and "444-12" means Column Address Strobe (CAS) latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.2 and produced on the Raw Card "A".
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Internet Data Sheet
HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
TABLE 3
Address Format
DIMM Density 1 GByte 2 GByte Module Organization 128M x 64 256M x 64 Memory Ranks 2 2 ECC/ Non-ECC Non-ECC Non-ECC # of SDRAMs # of row/bank/column bits 8 16 13/3/10 14/3/10 Raw Card A F
TABLE 4
Components on Modules
Product Type HYS64T128020EDL HYS64T256020EDL DRAM Components HYB18T1G160CF HYB18T1G800CF DRAM Density 1 Gbit 1 Gbit DRAM Organisation 64M x 16 128M x 8 Note1)2) -- --
1) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet. 2) Green Products
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Internet Data Sheet
HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
2
Pin Configuration
The pin configuration of the Small Outline DDR2 SDRAM DIMM is listed by function in Table 5 (200 pins). The abbreviations used in columns Pin Type and Buffer Type are explained in Table 6 and Table 7 respectively. The Pin numbering is depicted in Figure 1.
TABLE 5
Pin Configuration of SO-DIMM
Pin No. Clock Signals 30 164 32 166 79 80 CK0 CK1 CK0 CK1 CKE0 CKE1 NC Control Signals 110 115 S0 S1 NC 108 113 109 Address Signals 107 106 85 BA0 BA1 BA2 NC I I I NC SSTL SSTL SSTL SSTL Bank Address Bus 2 Greater than 512Mb DDR2 SDRAMS Less than 1Gb DDR2 SDRAMS Bank Address Bus 2:0 RAS CAS WE I I NC I I I SSTL SSTL -- SSTL SSTL SSTL Chip Select Rank 1:0 Note: 2 Ranks module Not Connected Note: 1-rank module Row Address Strobe Column Address Strobe Write Enable I I I I I I NC SSTL SSTL SSTL SSTL SSTL SSTL -- Clock Enable Rank 1:0 Note: 2 Ranks module Not Connected Note: 1-rank module Clock Signals 2:0, Complement Clock Signals 2:0 Name Pin Type Buffer Type Function
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Internet Data Sheet
HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
Pin No. 102 101 100 99 98 97 94 92 93 91 105 90 89 116
Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 AP A11 A12 A13 NC
Pin Type I I I I I I I I I I I I I I I NC
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL --
Function Address Bus 12:0
Address Signal 12 Note: Module based on 256 Mbit or larger dies Address Signal 13 Note: 1 Gbit based module Not Connected Note: Module based on 512 Mbit or smaller dies Data Bus 63:0 Note: Data Input/Output pins
Data Signals 5 7 17 19 4 6 14 16 23 25 35 37 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
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Internet Data Sheet
HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
Pin No. 20 22 36 38 43 45 55 57 44 46 56 58 61 63 73 75 62 64 74 76 123 125 135 137 124 126 134 136 141 143 151 153 140 142 152 154 157 159 173 175
Name DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51
Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
Function Data Bus 63:0 Data Input/Output pins
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Internet Data Sheet
HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
Pin No. 158 160 174 176 179 181 189 191 180 182 192 194 Data Strobe Signals 13 11 31 29 51 49 70 68 131 129 148 146 169 167 188 186 Data Mask Signals 10 26 52 67 130 147 170 185 EEPROM 197
Name DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQS0 DQS0 DQS1 DQS1 DQS2 DQS2 DQS3 DQS3 DQS4 DQS4 DQS5 DQS5 DQS6 DQS6 DQS7 DQS7 DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 SCL
Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I I
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL CMOS
Function Data Bus 63:0
Data Strobe Bus 7:0
Data Mask Bus 7:0
Serial Bus Clock
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HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
Pin No. 195 198 200 50 Power Supplies 1 199 81,82,87,88,95,96,103,104, 111,112,117,118
Name SDA SA0 SA1 EVENT NC
Pin Type I/O I I O -- AI PWR PWR GND
Buffer Type OD CMOS CMOS OD -- -- -- -- --
Function Serial Bus Data Serial Address Select Bus 2:0 EVENT Not Connected I/O Reference Voltage EEPROM Power Supply Power Supply Ground Plane
VREF VDDSPD VDD
2,3,8,9,12,15,18,21,24,27,28, VSS 33,34,39,40,41,42,47,48,53, 54,59,60,65,66,71,72,77,78, 121,122,127,128,132,133,138,13 9,144,145,149,150,155,156, 161,162,165,171,172,177, 178,183,184,187,190,193,196 Other pins 114 119 ODT0 ODT1 NC 69,83,84,120,163,168 NC
I I NC NC
SSTL SSTL -- --
On-Die Termination Control 1:0 On-Die Termination Control 1 Note: 2 Rank modules Not Connected Note: 1 Rank modules Not connected
TABLE 6
Abbreviations for pin Type
Abbreviation I O I/O AI PWR GND NC Description Standard input-only pin. Digital levels. Output. Digital levels. I/O is a bidirectional input/output signal. Input. Analog levels. Power Ground Not Connected
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HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
TABLE 7
Abbreviations for Buffer Type
Abbreviation SSTL LV-CMOS CMOS OD Description Serial Stub Terminated Logic (SSTL_18) Low Voltage CMOS CMOS Levels Open Drain. The corresponding pin has 2 operational states, active low and tri-state, and allows multiple devices to share as a wire-OR.
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Internet Data Sheet
HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
FIGURE 1
Pin Configuration SO-DIMM (200 pin)
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HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
3
3.1
Electrical Characteristics
Absolute Maximum Ratings
TABLE 8
Absolute Maximum Ratings
Caution is needed not to exceed absolute maximum ratings of the DRAM device listed in Table 8 at any time.
Symbol
Parameter
Rating Min. Max. +2.3 +2.3 +2.3 +2.3
Unit
Note
Storage Temperature -55 +100 1) When VDD and VDDQ and VDDL are less than 500 mV; VREF may be equal to or less than 300 mV.
2) Storage Temperature is the case surface temperature on the center/top side of the DRAM.
VDD VDDQ VDDL VIN, VOUT TSTG
Voltage on VDD pin relative to VSS Voltage on VDDQ pin relative to VSS Voltage on VDDL pin relative to VSS Voltage on any pin relative to VSS
-1.0 -0.5 -0.5 -0.5
V V V V C
1) 1)2) 1)2) 1) 1)2)
Attention: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
TABLE 9
DRAM Component Operating Temperature Range
Symbol Parameter Rating Min. Max. 95 C
1)2)3)4)
Unit
Note
TCASE
Operating Temperature
0
1) Operating Temperature is the case surface temperature on the center / top side of the DRAM. 2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case temperature must be maintained between 0 - 95 C under all other specification parameters. 3) Above 85 C the Auto-Refresh command interval has to be reduced to tREFI= 3.9 s 4) When operating this product in the 85 C to 95 C TCASE temperature range, the High Temperature Self Refresh has to be enabled by setting EMR(2) bit A7 to "1". When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50 %
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HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
3.2
DC Operating Conditions
TABLE 10
Operating Conditions
Parameter
Symbol
Values Min. Max. +65 +95 +100 +105 90
Unit
Note
Operating temperature (ambient) DRAM Case Temperature Storage Temperature Barometric Pressure (operating & storage) Operating Humidity (relative)
1) 2) 3) 4)
TOPR TCASE TSTG PBar HOPR
0 0 - 50 +69 10
C C C kPa %
--
1)2)3)4)
--
5)
--
DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs. Within the DRAM Component Case Temperature Range all DRAM specifications will be supported Above 85 C DRAM Case Temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 s When operating this product in the 85 C to 95 C TCASE temperature range, the High Temperature Self Refresh has to be enabled by setting EMR(2) bit A7 to "1". When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50 %. 5) Up to 3000 m.
TABLE 11
Supply Voltage Level
Parameter Symbol Values Min. Device Supply Voltage Output Supply Voltage Input Reference Voltage SPD Supply Voltage DC Input Logic High DC Input Logic Low Typ. 1.8 1.8 0.5 x VDDQ -- -- -- Max. 1.9 1.9 0.51 x VDDQ 3.6 V V V V V V --
1) 2)
Unit
Note
In / Output Leakage Current -5 -- 5 A 1) Under all conditions, VDDQ must be less than or equal to VDD 2) Peak to peak AC noise on VREF may not exceed 2 % VREF (DC).VREF is also expected to track noise in VDDQ. 3) Input voltage for any connector pin under test of 0 V VIN VDDQ + 0.3 V; all other pins at 0 V. Current is per pin
VDD VDDQ VREF VDDSPD VIH(DC) VIL (DC) IL
1.7 1.7 0.49 x VDDQ 1.7
-- -- --
3)
VREF + 0.125
- 0.30
VDDQ + 0.3 VREF - 0.125
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HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
3.3
AC Characteristics
3.3.1
Speed Grade Definitions
All Speed grades faster than DDR2-400B comply with DDR2-400B timing specifications(tCK = 5ns with tRAS = 40ns). Speed Grade Definitions for: DDR2-800 (Table 12), DDR2-667 (Table 13) and DDR2-533C (Table 14)
TABLE 12
Speed Grade Definition Speed Bins for DDR2-800
Speed Grade QAG Sort Name CAS-RCD-RP latencies Parameter Clock Frequency @ CL = 3 @ CL = 4 @ CL = 5 @ CL = 6 Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time Symbol DDR2-800D -2.5F 5-5-5 Min. 5 3.75 2.5 2.5 45 57.5 12.5 12.5 Max. 8 8 8 8 70000 -- -- -- DDR2-800E -2.5 6-6-6 Min. 5 3.75 3 2.5 45 60 15 15 Max. 8 8 8 8 70000 -- -- -- Unit Note
tCK
-- ns ns ns ns ns ns ns ns
1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4)5) 1)2)3)4) 1)2)3)4) 1)2)3)4)
tCK tCK tCK tCK tRAS tRC tRCD tRP
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) 2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode. 3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 4) The output timing reference voltage level is VTT. 5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
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HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
TABLE 13
Speed Grade Definition Speed Bins for DDR2-667
Speed Grade QAG Sort Name CAS-RCD-RP latencies Parameter Clock Frequency @ CL = 3 @ CL = 4 @ CL = 5 Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time Symbol DDR2-667C -3 4-4-4 Min. 5 3 3 45 57 12 12 Max. 8 8 8 70000 -- -- -- DDR2-667D -3S 5-5-5 Min. 5 3.75 3 45 60 15 15 Max. 8 8 8 70000 -- -- -- Unit Note
tCK
-- ns ns ns ns ns ns ns
1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4)5) 1)2)3)4) 1)2)3)4) 1)2)3)4)
tCK tCK tCK tRAS tRC tRCD tRP
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) . 2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode 3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 4) The output timing reference voltage level is VTT. 5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
TABLE 14
Speed Grade Definition Speed Bins for DDR2-533C
Speed Grade QAG Sort Name CAS-RCD-RP latencies Parameter Clock Frequency @ CL = 3 @ CL = 4 @ CL = 5 Row Active Time Row Cycle Time RAS-CAS-Delay Row Precharge Time Symbol DDR2-533C -3.7 4-4-4 Min. 5 3.75 3.75 45 60 15 15 Max. 8 8 8 70000 -- -- -- Unit Note
tCK
-- ns ns ns ns ns ns ns
1)2)3)4) 1)2)3)4) 1)2)3)4) 1)2)3)4)5) 1)2)3)4) 1)2)3)4) 1)2)3)4)
tCK tCK tCK tRAS tRC tRCD tRP
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.Timings are further guaranteed for normal OCD drive strength (EMRS(1) A1 = 0) 2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode. 3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 4) The output timing reference voltage level is VTT. 5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
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HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
3.3.2
Component AC Timing Parameters
TABLE 15
DRAM Component Timing Parameter by Speed Grade - DDR2-800
Timing Parameters for: DDR2-800 (Table 15), DDR2-667 (Table 16) and DDR2-533C (Table 17)
Parameter
Symbol
DDR2-800 Min. Max. +400 -- 0.52 8000 -- 0.52 -- -- -- -- +350 -- -- 200 + 0.25 -- -- -- -- -- __
Unit
Note1)2)3)4)5)6)7)
8)
DQ output access time from CK / CK CAS to CAS command delay Average clock high pulse width Average clock period CKE minimum pulse width ( high and low pulse width) Average clock low pulse width
tAC tCCD tCH.AVG tCK.AVG tCKE
-400 2 0.48 2500 3 0.48 WR + tnRP
ps nCK
9)
--
10)11) 10)11) 12)
tCK.AVG
ps nCK
tCL.AVG Auto-Precharge write recovery + precharge time tDAL Minimum time clocks remain ON after CKE tDELAY
asynchronously drops LOW DQ and DM input hold time
tCK.AVG
nCK ns ps ps
10)11) 13)14)
tIS + tCK .AVG + tIH
125 0.35 -350 0.35 0.35 -- - 0.25 50 0.2 0.2 35 45 Min (tCH.ABS, tCL.ABS) -- 250 0.6 175 2 x tAC.MIN
tDH.BASE DQ and DM input pulse width for each input tDIPW DQS output access time from CK / CK tDQSCK DQS input high pulse width tDQSH DQS input low pulse width tDQSL DQS-DQ skew for DQS & associated DQ signals tDQSQ DQS latching rising transition to associated clock tDQSS
edges
19)20)15)
tCK.AVG --
9)
tCK.AVG -- tCK.AVG --
ps
16) 17)
tCK.AVG
ps
tDS.BASE DQS falling edge hold time from CK tDSH DQS falling edge to CK setup time tDSS Four Activate Window for 1KB page size products tFAW Four Activate Window for 2KB page size products tFAW CK half pulse width tHP
DQ and DM input setup time
18)19)20) 17) 17) 31) 31) 21)
tCK.AVG tCK.AVG
ns ns ps ps ps ps ps ps ns nCK ns ps
tHZ Address and control input hold time tIH.BASE Control & address input pulse width for each input tIPW Address and control input setup time tIS.BASE DQ low impedance time from CK/CK tLZ.DQ DQS/DQS low-impedance time from CK / CK tLZ.DQS MRS command to ODT update delay tMOD Mode register set command cycle time tMRD tOIT OCD drive mode output delay DQ/DQS output hold time from DQS tQH
Data-out high-impedance time from CK / CK
tAC.MAX
-- -- --
9)22) 23)25)
tCK.AVG --
24)25) 9)22) 9)22) 31)
tAC.MIN
0 2 0
tAC.MAX tAC.MAX
12 -- 12 --
--
31) 26)
tHP - tQHS
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Internet Data Sheet
HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
Parameter
Symbol
DDR2-800 Min. Max. 300 1.1 0.6 -- -- -- -- 0.6 -- -- -- -- -- -- --
Unit
Note1)2)3)4)5)6)7)
8)
DQ hold skew factor Read preamble Read postamble Active to active command period for 1KB page size products Active to active command period for 2KB page size products Internal Read to Precharge command delay Write preamble Write postamble Write recovery time Internal write to read command delay Exit power down to read command Exit active power-down mode to read command (slow exit, lower power) Exit precharge power-down to any valid command (other than NOP or Deselect) Exit self-refresh to a non-read command Exit self-refresh to read command Write command to DQS associated clock edges
tQHS tRPRE tRPST tRRD tRRD tRTP tWPRE tWPST tWR tWTR tXARD tXARDS tXP tXSNR tXSRD
WL
-- 0.9 0.4 7.5 10 7.5 0.35 0.4 15 7.5 2 8 - AL 2
ps
27) 28)29) 28)30) 31)
tCK.AVG tCK.AVG
ns ns ns
31)
31)
tCK.AVG -- tCK.AVG --
ns ns nCK nCK nCK ns nCK nCK
31) 31)32)
-- -- --
31)
tRFC +10
200 RL - 1
-- --
1) For details and notes see the relevant Qimonda component data sheet 2) VDDQ = 1.8 V 0.1V; VDD = 1.8 V 0.1 V. 3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode. 6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 7) The output timing reference voltage level is VTT. 8) New units, `tCK.AVG` and `nCK`, are introduced in DDR2-667 and DDR2-800. Unit `tCK.AVG` represents the actual tCK.AVG of the input clock under operation. Unit `nCK` represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and DDR2-533, `tCK` is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min). 9) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tERR(6-10PER).MIN = - 272 ps and tERR(6- 10PER).MAX = + 293 ps, then tDQSCK.MIN(DERATED) = tDQSCK.MIN - tERR(6-10PER).MAX = - 400 ps - 293 ps = - 693 ps and tDQSCK.MAX(DERATED) = tDQSCK.MAX - tERR(6-10PER).MIN = 400 ps + 272 ps = + 672 ps. Similarly, tLZ.DQ for DDR2-667 derates to tLZ.DQ.MIN(DERATED) = - 900 ps - 293 ps = - 1193 ps and tLZ.DQ.MAX(DERATED) = 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!) 10) Input clock jitter spec parameter. These parameters are referred to as 'input clock jitter spec parameters' and these parameters apply to DDR2-667 and DDR2-800 only. The jitter specified is a random jitter meeting a Gaussian distribution. 11) These parameters are specified per their average values, however it is understood that the relationship between the average timing and the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations). 12) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2 x tCK + tIH.
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Internet Data Sheet
HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
13) DAL = WR + RU{tRP(ns) / tCK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result of the division is not already an integer, round up to the next highest integer. tCK refers to the application clock period. Example: For DDR2-533 at tCK = 3.75 ns with tWR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks. 14) tDAL.nCK = WR [nCK] + tnRP.nCK = WR + RU{tRP [ps] / tCK.AVG[ps] }, where WR is the value programmed in the EMR. 15) Input waveform timing tDH with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to the input signal crossing at the VIH.DC level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the VIL.DC level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between VIL.DC.MAX and VIH.DC.MIN. See Figure 3. 16) tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate mismatch between DQS / DQS and associated DQ in any given cycle. 17) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or not. 18) Input waveform timing tDS with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the VIH.AC level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL.AC level to the differential data strobe crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(DC)MAX and Vih(DC)MIN. See Figure 3. 19) If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed. 20) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal ((L/U/R)DQS / DQS) crossing. 21) tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter. It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the following equation; tHP = MIN (tCH.ABS, tCL.ABS), where, tCH.ABS is the minimum of the actual instantaneous clock high time; tCL.ABS is the minimum of the actual instantaneous clock low time. 22) tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) . 23) Input waveform timing is referenced from the input signal crossing at the VIL.DC level for a rising signal and VIH.DC for a falling signal applied to the device under test. See Figure 4. 24) Input waveform timing is referenced from the input signal crossing at the VIH.AC level for a rising signal and VIL.AC for a falling signal applied to the device under test. See Figure 4. 25) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should be met whether clock jitter is present or not. 26) tQH = tHP - tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under the max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.} Examples: 1) If the system provides tHP of 1315 ps into a DDR2-667 SDRAM, the DRAM provides tQH of 975 ps minimum. 2) If the system provides tHP of 1420 ps into a DDR2-667 SDRAM, the DRAM provides tQH of 1080 ps minimum. 27) tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation of the output drivers. 28) tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST), or begins driving (tRPRE). Figure 2 shows a method to calculate these points when the device is no longer driving (tRPST), or begins driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. 29) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.PER of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tJIT.PER.MIN = - 72 ps and tJIT.PER.MAX = + 93 ps, then tRPRE.MIN(DERATED) = tRPRE.MIN + tJIT.PER.MIN = 0.9 x tCK.AVG - 72 ps = + 2178 ps and tRPRE.MAX(DERATED) = tRPRE.MAX + tJIT.PER.MAX = 1.1 x tCK.AVG + 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!). 30) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.DUTY of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tJIT.DUTY.MIN = - 72 ps and tJIT.DUTY.MAX = + 93 ps, then tRPST.MIN(DERATED) = tRPST.MIN + tJIT.DUTY.MIN = 0.4 x tCK.AVG - 72 ps = + 928 ps and tRPST.MAX(DERATED) = tRPST.MAX + tJIT.DUTY.MAX = 0.6 x tCK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!). 31) For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK.AVG}, which is in clock cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK.AVG}, which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR2-667 5-5-5, of which tRP = 15 ns, the device will support tnRP = RU{tRP / tCK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter. 32) tWTR is at lease two clocks (2 x tCK) independent of operation frequency.
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Internet Data Sheet
HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
TABLE 16
DRAM Component Timing Parameter by Speed Grade - DDR2-667
Parameter Symbol DDR2-667 Min. DQ output access time from CK / CK CAS to CAS command delay Average clock high pulse width Average clock period CKE minimum pulse width ( high and low pulse width) Average clock low pulse width Max. +450 -- 0.52 8000 -- 0.52 -- -- -- -- +400 -- -- 240 + 0.25 -- -- -- -- -- __ ps nCK
9)
Unit
Note1)2)3)4)5)6)7)
8)
tAC tCCD tCH.AVG tCK.AVG tCKE
-450 2 0.48 3000 3 0.48 WR + tnRP
--
10)11)
tCK.AVG
ps nCK
12)
tCL.AVG Auto-Precharge write recovery + precharge time tDAL Minimum time clocks remain ON after CKE tDELAY
asynchronously drops LOW DQ and DM input hold time
tCK.AVG
nCK ns ps ps
10)11) 13)14)
tIS + tCK .AVG + tIH
175 0.35 -400 0.35 0.35 -- - 0.25 100 0.2 0.2 37.5 50 Min (tCH.ABS, tCL.ABS) -- 275 0.6 200 2 x tAC.MIN
tDH.BASE DQ and DM input pulse width for each input tDIPW tDQSCK DQS output access time from CK / CK DQS input high pulse width tDQSH DQS input low pulse width tDQSL DQS-DQ skew for DQS & associated DQ signals tDQSQ DQS latching rising transition to associated clock tDQSS
edges
19)20)15)
tCK.AVG --
9)
tCK.AVG -- tCK.AVG --
ps
16) 17)
tCK.AVG
ps
tDS.BASE DQS falling edge hold time from CK tDSH DQS falling edge to CK setup time tDSS Four Activate Window for 1KB page size products tFAW Four Activate Window for 2KB page size products tFAW CK half pulse width tHP
DQ and DM input setup time
18)19)20) 17) 17) 31) 31) 21)
tCK.AVG tCK.AVG
ns ns ps ps ps ps ps ps ns nCK ns ps ps
tHZ Address and control input hold time tIH.BASE Control & address input pulse width for each input tIPW Address and control input setup time tIS.BASE DQ low impedance time from CK/CK tLZ.DQ DQS/DQS low-impedance time from CK / CK tLZ.DQS MRS command to ODT update delay tMOD Mode register set command cycle time tMRD OCD drive mode output delay tOIT DQ/DQS output hold time from DQS tQH DQ hold skew factor tQHS Read preamble tRPRE Read postamble tRPST
Data-out high-impedance time from CK / CK
tAC.MAX
-- -- --
9)22) 25)23)
tCK.AVG --
24)25) 9)22) 9)22) 31)
tAC.MIN
0 2 0
tAC.MAX tAC.MAX
12 -- 12 -- 340 1.1 0.6
--
31) 26) 27) 28)29) 28)30)
tHP - tQHS
-- 0.9 0.4
tCK.AVG tCK.AVG
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Internet Data Sheet
HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
Parameter
Symbol
DDR2-667 Min. Max. -- -- -- -- 0.6 -- -- -- -- -- -- --
Unit
Note1)2)3)4)5)6)7)
8)
Active to active command period for 1KB page size products Active to active command period for 2KB page size products Internal Read to Precharge command delay Write preamble Write postamble Write recovery time Internal write to read command delay Exit power down to read command Exit active power-down mode to read command (slow exit, lower power) Exit precharge power-down to any valid command (other than NOP or Deselect) Exit self-refresh to a non-read command Exit self-refresh to read command Write command to DQS associated clock edges
tRRD tRRD tRTP tWPRE tWPST tWR tWTR tXARD tXARDS tXP tXSNR tXSRD
WL
7.5 10 7.5 0.35 0.4 15 7.5 2 7 - AL 2
ns ns ns
31)
31)
31)
tCK.AVG -- tCK.AVG --
ns ns nCK nCK nCK ns nCK nCK
31) 31)32)
-- -- --
31)
tRFC +10
200 RL-1
-- --
1) For details and notes see the relevant Qimonda component data sheet 2) VDDQ = 1.8 V 0.1V; VDD = 1.8 V 0.1 V. 3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode. 6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 7) The output timing reference voltage level is VTT. 8) New units, `tCK.AVG` and `nCK`, are introduced in DDR2-667 and DDR2-800. Unit `tCK.AVG` represents the actual tCK.AVG of the input clock under operation. Unit `nCK` represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and DDR2-533, `tCK` is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min). 9) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tERR(6-10PER).MIN = - 272 ps and tERR(6- 10PER).MAX = + 293 ps, then tDQSCK.MIN(DERATED) = tDQSCK.MIN - tERR(6-10PER).MAX = - 400 ps - 293 ps = - 693 ps and tDQSCK.MAX(DERATED) = tDQSCK.MAX - tERR(6-10PER).MIN = 400 ps + 272 ps = + 672 ps. Similarly, tLZ.DQ for DDR2-667 derates to tLZ.DQ.MIN(DERATED) = - 900 ps - 293 ps = - 1193 ps and tLZ.DQ.MAX(DERATED) = 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!) 10) Input clock jitter spec parameter. These parameters are referred to as 'input clock jitter spec parameters' and these parameters apply to DDR2-667 and DDR2-800 only. The jitter specified is a random jitter meeting a Gaussian distribution. 11) These parameters are specified per their average values, however it is understood that the relationship between the average timing and the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations). 12) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + 2 x tCK + tIH. 13) DAL = WR + RU{tRP(ns) / tCK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result of the division is not already an integer, round up to the next highest integer. tCK refers to the application clock period. Example: For DDR2-533 at tCK = 3.75 ns with tWR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks. 14) tDAL.nCK = WR [nCK] + tnRP.nCK = WR + RU{tRP [ps] / tCK.AVG[ps] }, where WR is the value programmed in the EMR.
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Internet Data Sheet
HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
15) Input waveform timing tDH with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to the input signal crossing at the VIH.DC level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the VIL.DC level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between VIL.DC.MAX and VIH.DC.MIN. See Figure 3. 16) tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate mismatch between DQS / DQS and associated DQ in any given cycle. 17) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or not. 18) Input waveform timing tDS with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the VIH.AC level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL.AC level to the differential data strobe crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(DC)MAX and Vih(DC)MIN. See Figure 3. 19) If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed. 20) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal ((L/U/R)DQS / DQS) crossing. 21) tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter. It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the following equation; tHP = MIN (tCH.ABS, tCL.ABS), where, tCH.ABS is the minimum of the actual instantaneous clock high time; tCL.ABS is the minimum of the actual instantaneous clock low time. 22) tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) . 23) Input waveform timing is referenced from the input signal crossing at the VIL.DC level for a rising signal and VIH.DC for a falling signal applied to the device under test. See Figure 4. 24) Input waveform timing is referenced from the input signal crossing at the VIH.AC level for a rising signal and VIL.AC for a falling signal applied to the device under test. See Figure 4. 25) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should be met whether clock jitter is present or not. 26) tQH = tHP - tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under the max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.} Examples: 1) If the system provides tHP of 1315 ps into a DDR2-667 SDRAM, the DRAM provides tQH of 975 ps minimum. 2) If the system provides tHP of 1420 ps into a DDR2-667 SDRAM, the DRAM provides tQH of 1080 ps minimum. 27) tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation of the output drivers. 28) tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST), or begins driving (tRPRE). Figure 2 shows a method to calculate these points when the device is no longer driving (tRPST), or begins driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. 29) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.PER of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tJIT.PER.MIN = - 72 ps and tJIT.PER.MAX = + 93 ps, then tRPRE.MIN(DERATED) = tRPRE.MIN + tJIT.PER.MIN = 0.9 x tCK.AVG - 72 ps = + 2178 ps and tRPRE.MAX(DERATED) = tRPRE.MAX + tJIT.PER.MAX = 1.1 x tCK.AVG + 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!). 30) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.DUTY of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2-667 SDRAM has tJIT.DUTY.MIN = - 72 ps and tJIT.DUTY.MAX = + 93 ps, then tRPST.MIN(DERATED) = tRPST.MIN + tJIT.DUTY.MIN = 0.4 x tCK.AVG - 72 ps = + 928 ps and tRPST.MAX(DERATED) = tRPST.MAX + tJIT.DUTY.MAX = 0.6 x tCK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!). 31) For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK.AVG}, which is in clock cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK.AVG}, which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR2-667 5-5-5, of which tRP = 15 ns, the device will support tnRP = RU{tRP / tCK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter. 32) tWTR is at lease two clocks (2 x tCK) independent of operation frequency.
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Internet Data Sheet
HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
FIGURE 2
Method for calculating transitions and endpoint
FIGURE 3
Differential input waveform timing - tDS and tDS
FIGURE 4
Differential input waveform timing - tlS and tlH
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Internet Data Sheet
HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
TABLE 17
DRAM Component Timing Parameter by Speed Grade - DDR2-533
Parameter Symbol DDR2-533 Min. DQ output access time from CK / CK CAS A to CAS B command period CK, CK high-level width CKE minimum high and low pulse width CK, CK low-level width Auto-Precharge write recovery + precharge time Minimum time clocks remain ON after CKE asynchronously drops LOW DQ and DM input hold time (differential data strobe) Max. +500 -- 0.55 -- 0.55 -- -- -- -- -- +450 -- 300 + 0.25 -- -- -- -- -- -- ps -- -- -- -- --
8)18)
Unit
Note1)2)3)4)5)
6)7)
tAC tCCD tCH tCKE tCL tDAL tDELAY tDH(base)
-500 2 0.45 3 0.45 WR + tRP
tCK tCK tCK tCK tCK
ns ps ps
tIS + tCK + tIH
225 -25 0.35 -450 0.35 -- - 0.25 100 -25 0.2 0.2 37.5 50 MIN. (tCL, tCH) -- 375 0.6 250 2 x tAC.MIN
9)
10)
DQ and DM input hold time (single ended data tDH1(base) strobe) DQ and DM input pulse width (each input) DQS output access time from CK / CK DQS input low (high) pulse width (write cycle) DQS-DQ skew (for DQS & associated DQ signals) Write command to 1st DQS latching transition DQ and DM input setup time (differential data strobe)
11)
tDIPW tDQSCK tDQSL,H tDQSQ tDQSS tDS(base)
tCK
ps
-- -- --
11)
tCK
ps
tCK
ps ps
--
11)
DQ and DM input setup time (single ended data tDS1(base) strobe) DQS falling edge hold time from CK (write cycle) Four Activate Window period Four Activate Window period Clock half period Data-out high-impedance time from CK / CK Address and control input hold time Address and control input pulse width (each input) Address and control input setup time DQ low-impedance time from CK / CK DQS low-impedance from CK / CK Mode register set command cycle time OCD drive mode output delay Data output hold time from DQS
11)
tDSH
tCK tCK
ns ns -- ps ps
-- -- --
13) 12) 13) 11)
DQS falling edge to CK setup time (write cycle) tDSS
tFAW tFAW tHP tHZ tIH(base) tIPW tIS(base) tLZ(DQ) tLZ(DQS) tMRD tOIT tQH
tAC.MAX
-- -- --
tCK
ps ps ps
--
11) 14) 14)
tAC.MIN
2 0
tAC.MAX tAC.MAX
-- 12 --
tCK
ns --
-- -- --
tHP -tQHS
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HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
Parameter
Symbol
DDR2-533 Min. Max. 400 7.8 3.9 --
Unit
Note1)2)3)4)5)
6)7)
Data hold skew factor Average periodic refresh Interval Average periodic refresh Interval Auto-Refresh to Active/Auto-Refresh command period Precharge-All (4 banks) command period Precharge-All (8 banks) command period Read preamble Read postamble Active bank A to Active bank B command period Active bank A to Active bank B command period Internal Read to Precharge command delay Write preamble Write postamble Write recovery time for write without AutoPrecharge Internal Write to Read command delay Exit power down to any valid command (other than NOP or Deselect) Exit active power-down mode to Read command (slow exit, lower power) Exit precharge power-down to any valid command (other than NOP or Deselect) Exit Self-Refresh to non-Read command Exit Self-Refresh to Read command Write recovery time for write with AutoPrecharge
tQHS tREFI tREFI tRFC tRP tRP tRPRE tRPST tRRD tRRD tRTP tWPRE tWPST tWR tWTR tXARD tXARDS tXP tXSNR tXSRD
WR
-- -- --
ps s s ns ns ns
--
14)15) 16)18) 17)
tRP + 1tCK
15 + 1tCK 0.9 0.40 7.5 10 7.5 0.25 0.40 15 7.5 2 6 - AL 2
-- -- 1.1 0.60 -- -- -- -- 0.60 -- -- -- -- -- -- -- --
-- --
14) 14) 14)18)
tCK tCK
ns ns ns
16)22)
-- --
19)
tCK tCK
ns ns
--
20) 21)
tCK tCK tCK
ns
21)
-- -- --
22)
tRFC +10
200
tWR/tCK
tCK tCK
1) For details and notes see the relevant Qimonda component data sheet 2) VDDQ = 1.8 V 0.1 V; VDD = 1.8 V 0.1 V. 3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down and then restarted through the specified initialization sequence before normal operation can continue. 4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. 5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode. 6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low. 7) The output timing reference voltage level is VTT. 8) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MR. 9) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. 10) For timing definition, refer to the Component data sheet. 11) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate mis-match between DQS / DQS and associated DQ in any given cycle.
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HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
12) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). 13) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving (tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These parameters are verified by design and characterization, but not subject to production test. 14) The Auto-Refresh command interval has be reduced to 3.9 s when operating the DDR2 DRAM in a temperature range between 85 C and 95 C. 15) 0 C TCASE 85 C 16) 85 C < TCASE 95 C 17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device. 18) The tRRD timing parameter depends on the page size of the DRAM organization. See Table 2 "Ordering Information for RoHS Compliant Products" on Page 4. 19) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 20) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies 200 z. 21) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In "standard active powerdown mode" (MR, A12 = "0") a fast power-down exit timing tXARD can be used. In "low active power-down mode" (MR, A12 ="1") a slow power-down exit timing tXARDS has to be satisfied. 22) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR parameter stored in the MRS.
3.3.3
ODT AC Electrical Characteristics
TABLE 18
ODT AC Characteristics and Operating Conditions for DDR2-667 & DDR2-800
This chapter describes the ODT AC electrical characteristics.
Symbol
Parameter / Condition
Values Min. Max. 2
Unit
Note
tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD
ODT turn-on delay ODT turn-on ODT turn-on (Power-Down Modes) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down Modes) ODT to Power Down Mode Entry Latency ODT Power Down Exit Latency
2
nCK
ns ns
1) 1)2) 1) 1) 1)3) 1) 1) 1)
tAC.MIN tAC.MIN + 2 ns
2.5
tAC.MAX + 0.7 ns 2 tCK + tAC.MAX + 1 ns
2.5
nCK
ns ns
tAC.MIN tAC.MIN + 2 ns
3 8
tAC.MAX + 0.6 ns 2.5 tCK + tAC.MAX + 1 ns
-- --
nCK nCK
1) New units, "tCK.AVG" and "nCK", are introduced in DDR2-667 and DDR2-800. Unit "tCK.AVG" represents the actual tCK.AVG of the input clock under operation. Unit "nCK" represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and DDR2-533, "tCK" is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min). 2) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-667/800, tAOND is 2 clock cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges. 3) ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-667/800, if tCK(avg) = 3 ns is assumed, tAOFD is 1.5 ns (= 0.5 x 3 ns) after the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by counting the actual input clock edges.
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HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
TABLE 19
ODT AC Characteristics and Operating Conditions for DDR2-533
Symbol Parameter / Condition Values Min. Max. 2 Unit Note
tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD
ODT turn-on delay ODT turn-on ODT turn-on (Power-Down Modes) ODT turn-off delay ODT turn-off ODT turn-off (Power-Down Modes) ODT to Power Down Mode Entry Latency ODT Power Down Exit Latency
2
tCK
ns ns
--
1)
tAC.MIN tAC.MIN + 2 ns
2.5
tAC.MAX + 1 ns 2 tCK + tAC.MAX + 1 ns
2.5
-- --
2)
tCK
ns ns
tAC.MIN tAC.MIN + 2 ns
3 8
tAC.MAX + 0.6 ns 2.5 tCK + tAC.MAX + 1 ns
-- --
-- -- --
tCK tCK
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-400/533, tAOND is 10 ns (= 2 x 5 ns) after the clock edge that registered a first ODT HIGH if tCK = 5 ns. 2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD. Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-400/533, tAOFD is 12.5 ns (= 2.5 x 5 ns) after the clock edge that registered a first ODT HIGH if tCK = 5 ns.
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HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
3.4
IDD Specifications and Conditions
List of tables defining IDD Specifications and Conditions. * Table 20 "IDD Measurement Conditions" on Page 28 * Table 21 "Definitions for IDD" on Page 29 * Table 22 "IDD Specification for HYS64T[128/256]020EDL-[25F/2.5/3]-C" on Page 30 * Table 23 "IDD Specification for HYS64T[128/256]020EDL-[3S/3.7]-C" on Page 31
TABLE 20
IDD Measurement Conditions
Parameter Symbol Note
1)2)3)4)5)
Operating Current 0 IDD0 One bank Active - Precharge; tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING. Operating Current 1 One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, tRCD = tRCD.MIN, AL = 0, CL = CLMIN; CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
IDD1
6)
Precharge Standby Current IDD2N All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are SWITCHING, Databus inputs are SWITCHING. Precharge Power-Down Current Other control and address inputs are STABLE, Data bus inputs are FLOATING. Precharge Quiet Standby Current All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are STABLE, Data bus inputs are FLOATING. Active Standby Current Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN; tRAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
IDD2P IDD2Q
IDD3N
Active Power-Down Current IDD3P(0) All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit); Active Power-Down Current IDD3P(1) All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit); Operating Current - Burst Read IDD4R All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCKMIN; tRAS = tRASMAX; tRP = tRPMIN; CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data bus inputs are SWITCHING; IOUT = 0mA. Operating Current - Burst Write All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN; tRAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; Burst Refresh Current tCK = tCK.MIN., Refresh command every tRFC = tRFC.MIN interval, CKE is HIGH, CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
6)
IDD4W
IDD5B
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HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
Parameter Distributed Refresh Current tCK = tCK.MIN., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Symbol Note
1)2)3)4)5)
IDD5D
Self-Refresh Current IDD6 CKE 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data bus inputs are FLOATING. IDD6 current values are guaranteed up to TCASE of 85 C max.
6) All Bank Interleave Read Current IDD7 All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control and address bus inputs are STABLE during DESELECTS. Iout = 0 mA. 1) VDDQ = 1.8 V 0.1 V; VDD = 1.8 V 0.1 V 2) IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled. 3) Definitions for IDD see Table 21 4) For two rank modules: All active current measurements in the same IDD current mode. The other rank is in IDD2P Precharge Power-Down
Mode 5) For details and notes see the relevant Qimonda component data sheet 6) IDD1, IDD4R and IDD7 current measurements are defined with the outputs disabled (IOUT = 0 mA). To achieve this on module level the output buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.
TABLE 21
Definitions for IDD
Parameter LOW STABLE FLOATING SWITCHING Description
VIN VIL(ac).MAX, HIGH is defined as VIN VIH(ac).MIN
Inputs are stable at a HIGH or LOW level Inputs are VREF = VDDQ /2 Inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ signals not including mask or strobes
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HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
TABLE 22
IDD Specification for HYS64T[128/256]020EDL-[25F/2.5/3]-C
HYS64T128020EDL-25F-C HYS64T256020EDL-25F-C HYS64T128020EDL-2.5-C HYS64T256020EDL-2.5-C HYS64T128020EDL-3-C HYS64T256020EDL-3-C Product Type Unit Note1)
Organization
1GB 2 Rank x64 -25F
2GB 2 Rank x64 -25F Max. 824 856 1072 160 992 1152 560 240 1276 1336 1648 192 96 1776
1GB 2 Rank x64 -2.5 Max. 472 496 536 80 496 576 280 120 760 820 824 96 48
2GB 2 Rank x64 -2.5 Max. 820 850 1070 160 990 1150 560 240 1300 1340 1650 190 96
1GB 2 Rank x64 -3 Max. 450 480 500 80 460 520 260 120 680 740 790 100 48
2GB 2 Rank x64 -3 Max. 768 800 992 160 912 1040 528 240 1168 1208 1584 192 96 mA mA mA mA mA mA mA mA mA mA mA mA mA
2) 2) 3) 3) 3) 3)4) 3) 3)5) 2) 2) 2) 3)6) 3)6) 2)
Symbol
Max. 476 500 536 80 496 576 280 120 760 820 824 96 48 1112
1112 1780 1012 1640 mA 1) Calculated values from component data. ODT disabled. IDD1, IDD4R and IDD7 are defined with the outputs disabled. 2) The other rank is in IDD2P Precharge Power-Down Current mode 3) Both ranks are in the same IDDcurrent mode
4) Slow: MRS(12)=1 5) Fast: MRS(12)=0 6) IDD5D and IDD6 values are for 0 C TCase 85 C
IDD0 IDD1 IDD2N IDD2P IDD2Q IDD3N IDD3P( MRS = 0) IDD3P( MRS = 1) IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
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HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
TABLE 23
IDD Specification for HYS64T[128/256]020EDL-[3S/3.7]-C
HYS64T128020EDL-3.7-C HYS64T256020EDL-3.7-C HYS64T128020EDL-3S-C HYS64T256020EDL-3S-C Product Type Unit Note1)
Organization
1GB 2 Rank x64 -3S
2GB 2 Rank x64 -3S Max. 768 800 992 160 912 1040 528 240 1168 1208 1584 192 96
1GB 2 Rank x64 -3.7 Max. 424 448 440 80 432 464 240 120 608 660 780 96 48
2GB 2 Rank x64 -3.7 Max. 720 740 880 160 860 930 480 240 1040 1080 1560 190 96 mA mA mA mA mA mA mA mA mA mA mA mA mA
2) 2) 3) 3) 3) 3)4) 3) 3)5) 2) 2) 2) 3)6) 3)6) 2)
Symbol
Max. 448 476 496 80 456 520 264 120 684 740 792 96 48 1012
1624 980 1640 mA 1) Calculated values from component data. ODT disabled. IDD1, IDD4R and IDD7 are defined with the outputs disabled. 2) The other rank is in IDD2P Precharge Power-Down Current mode 3) Both ranks are in the same IDDcurrent mode
4) Slow: MRS(12) = 1 5) Fast: MRS(12) = 0 6) IDD5D and IDD6 values are for 0 C TCase 85 C
IDD0 IDD1 IDD2N IDD2P IDD2Q IDD3N IDD3P( MRS = 0) IDD3P( MRS = 1) IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
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HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
4
SPD Codes
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands for serial presence detect. All values with XX in the table are module specific bytes which are defined during production. List of SPD Code Tables * Table 24 "SPD codes for PC2-6400" on Page 32 * Table 25 "SPD codes for PC2-5300" on Page 37 * Table 26 "SPD codes for PC2-4200" on Page 42
TABLE 24
SPD codes for PC2-6400
HYS64T128020EDL-25F-C HYS64T128020EDL-2.5-C HYS64T256020EDL-2.5-C 2 GByte x64 2 Ranks (x8) PC2- 6400S-666 Rev. 1.2 HEX 80 08 08 0E 0A 61 40 00 05 25 40 Product Type HYS64T256020EDL-25F-C 2 GByte x64
Organization
1 GByte x64 2 Ranks (x16)
1 GByte x64
2 Ranks (x8) 2 Ranks (x16) PC2- 6400S-555 Rev. 1.2 HEX 80 08 08 0E 0A 61 40 00 05 25 40 PC2- 6400S-666 Rev. 1.2 HEX 80 08 08 0D 0A 61 40 00 05 25 40
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 Description Programmed SPD Bytes in EEPROM Total number of Bytes in EEPROM Memory Type (DDR2) Number of Row Addresses Number of Column Addresses DIMM Rank and Stacking Information Data Width Not used Interface Voltage Level
PC2- 6400S-555 Rev. 1.2 HEX 80 08 08 0D 0A 61 40 00 05 25 40
tCK @ CLMAX (Byte 18) [ns] tAC SDRAM @ CLMAX (Byte 18) [ns]
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HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
HYS64T128020EDL-25F-C
HYS64T128020EDL-2.5-C
Organization
1 GByte x64 2 Ranks (x16)
2 GByte x64
1 GByte x64
2 GByte x64 2 Ranks (x8) PC2- 6400S-666 Rev. 1.2 HEX 00 82 08 00 00 0C 08 70 01 04 00 07 30 45 3D 50 3C 1E 3C 2D 01 17 25 05
2 Ranks (x8) 2 Ranks (x16) PC2- 6400S-555 Rev. 1.2 HEX 00 82 08 00 00 0C 08 70 01 04 00 07 25 40 3D 50 32 1E 32 2D 01 17 25 05 PC2- 6400S-666 Rev. 1.2 HEX 00 82 10 00 00 0C 08 70 01 04 00 07 30 45 3D 50 3C 28 3C 2D 80 17 25 05
Label Code JEDEC SPD Revision Byte# 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Description Error Correction Support (non-ECC, ECC) Refresh Rate and Type Primary SDRAM Width Error Checking SDRAM Width Not used Burst Length Supported Number of Banks on SDRAM Device Supported CAS Latencies DIMM Mechanical Characteristics DIMM Type Information DIMM Attributes Component Attributes
PC2- 6400S-555 Rev. 1.2 HEX 00 82 10 00 00 0C 08 70 01 04 00 07 25 40 3D 50 32 28 32 2D 80 17 25 05
tCK @ CLMAX -1 (Byte 18) [ns] tAC SDRAM @ CLMAX -1 [ns] tCK @ CLMAX -2 (Byte 18) [ns] tAC SDRAM @ CLMAX -2 [ns] tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns] tRAS.MIN [ns]
Module Density per Rank
tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns]
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HYS64T256020EDL-2.5-C
Product Type
HYS64T256020EDL-25F-C
Internet Data Sheet
HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
HYS64T128020EDL-25F-C
HYS64T128020EDL-2.5-C
Organization
1 GByte x64 2 Ranks (x16)
2 GByte x64
1 GByte x64
2 GByte x64 2 Ranks (x8) PC2- 6400S-666 Rev. 1.2 HEX 12 3C 1E 1E 00 06 3C 7F 80 14 1E 00 51 60 4F 3D 3D 2C 35 24 46 24 27 00
2 Ranks (x8) 2 Ranks (x16) PC2- 6400S-555 Rev. 1.2 HEX 12 3C 1E 1E 00 06 39 7F 80 14 1E 00 51 60 4F 3D 3D 2C 35 24 46 24 27 00 PC2- 6400S-666 Rev. 1.2 HEX 12 3C 1E 1E 00 06 3C 7F 80 14 1E 00 53 58 57 38 38 28 3B 32 4C 21 2D 00
Label Code JEDEC SPD Revision Byte# 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 Description
PC2- 6400S-555 Rev. 1.2 HEX 12 3C 1E 1E 00 06 39 7F 80 14 1E 00 53 58 57 38 38 28 3B 32 4C 21 2D 00
tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns]
Analysis Characteristics
tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns]
PLL Relock Time
TCASE.MAX Delta / T4R4W Delta
Psi(T-A) DRAM T0 (DT0) T2N (DT2N, UDIMM) or T2Q (DT2Q, RDIMM) T2P (DT2P) T3N (DT3N) T3P.fast (DT3P fast) T3P.slow (DT3P slow) T4R (DT4R) / T4R4W Sign (DT4R4W) T5B (DT5B) T7 (DT7) Psi(ca) PLL
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HYS64T256020EDL-2.5-C
Product Type
HYS64T256020EDL-25F-C
Internet Data Sheet
HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
HYS64T128020EDL-25F-C
HYS64T128020EDL-2.5-C
Organization
1 GByte x64 2 Ranks (x16)
2 GByte x64
1 GByte x64
2 GByte x64 2 Ranks (x8) PC2- 6400S-666 Rev. 1.2 HEX 00 00 00 12 73 7F 7F 7F 7F 7F 51 00 00 xx 36 34 54 32 35 36 30 32 30 45
2 Ranks (x8) 2 Ranks (x16) PC2- 6400S-555 Rev. 1.2 HEX 00 00 00 12 4C 7F 7F 7F 7F 7F 51 00 00 xx 36 34 54 32 35 36 30 32 30 45 PC2- 6400S-666 Rev. 1.2 HEX 00 00 00 12 14 7F 7F 7F 7F 7F 51 00 00 xx 36 34 54 31 32 38 30 32 30 45
Label Code JEDEC SPD Revision Byte# 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 Description Psi(ca) REG TPLL (DTPLL) TREG (DTREG) / Toggle Rate SPD Revision Checksum of Bytes 0-62 Manufacturer's JEDEC ID Code (1) Manufacturer's JEDEC ID Code (2) Manufacturer's JEDEC ID Code (3) Manufacturer's JEDEC ID Code (4) Manufacturer's JEDEC ID Code (5) Manufacturer's JEDEC ID Code (6) Manufacturer's JEDEC ID Code (7) Manufacturer's JEDEC ID Code (8) Module Manufacturer Location Product Type, Char 1 Product Type, Char 2 Product Type, Char 3 Product Type, Char 4 Product Type, Char 5 Product Type, Char 6 Product Type, Char 7 Product Type, Char 8 Product Type, Char 9 Product Type, Char 10
PC2- 6400S-555 Rev. 1.2 HEX 00 00 00 12 ED 7F 7F 7F 7F 7F 51 00 00 xx 36 34 54 31 32 38 30 32 30 45
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HYS64T256020EDL-2.5-C
Product Type
HYS64T256020EDL-25F-C
Internet Data Sheet
HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
HYS64T128020EDL-25F-C
HYS64T128020EDL-2.5-C
Organization
1 GByte x64 2 Ranks (x16)
2 GByte x64
1 GByte x64
2 GByte x64 2 Ranks (x8) PC2- 6400S-666 Rev. 1.2 HEX 44 4C 32 2E 35 43 20 20 1x xx xx xx xx 00 FF
2 Ranks (x8) 2 Ranks (x16) PC2- 6400S-555 Rev. 1.2 HEX 44 4C 32 35 46 43 20 20 1x xx xx xx xx 00 FF PC2- 6400S-666 Rev. 1.2 HEX 44 4C 32 2E 35 43 20 20 1x xx xx xx xx 00 FF
Label Code JEDEC SPD Revision Byte# 83 84 85 86 87 88 89 90 91 92 93 94 95 - 98 128 255 Description Product Type, Char 11 Product Type, Char 12 Product Type, Char 13 Product Type, Char 14 Product Type, Char 15 Product Type, Char 16 Product Type, Char 17 Product Type, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number Blank for customer use
PC2- 6400S-555 Rev. 1.2 HEX 44 4C 32 35 46 43 20 20 1x xx xx xx xx 00 FF
99 - 127 Not used
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HYS64T256020EDL-2.5-C
Product Type
HYS64T256020EDL-25F-C
Internet Data Sheet
HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
TABLE 25
SPD codes for PC2-5300
HYS64T128020EDL-3S-C HYS64T128020EDL-3-C HYS64T256020EDL-3-C Product Type HYS64T256020EDL-3S-C 2 GByte x64 2 Ranks (x8) PC2- 5300S-555 Rev. 1.2 HEX 80 08 08 0E 0A 61 40 00 05 30 45 00 82 08 00 00 0C 08 38 01 04 00
Organization
1 GByte x64 2 Ranks (x16)
2 GByte x64
1 GByte x64
2 Ranks (x8) 2 Ranks (x16) PC2- 5300S-444 Rev. 1.2 HEX 80 08 08 0E 0A 61 40 00 05 30 45 00 82 08 00 00 0C 08 38 01 04 00 PC2- 5300S-555 Rev. 1.2 HEX 80 08 08 0D 0A 61 40 00 05 30 45 00 82 10 00 00 0C 08 38 01 04 00
Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Description Programmed SPD Bytes in EEPROM Total number of Bytes in EEPROM Memory Type (DDR2) Number of Row Addresses Number of Column Addresses DIMM Rank and Stacking Information Data Width Not used Interface Voltage Level
PC2- 5300S-444 Rev. 1.2 HEX 80 08 08 0D 0A 61 40 00 05 30 45 00 82 10 00 00 0C 08 38 01 04 00
tCK @ CLMAX (Byte 18) [ns] tAC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC) Refresh Rate and Type Primary SDRAM Width Error Checking SDRAM Width Not used Burst Length Supported Number of Banks on SDRAM Device Supported CAS Latencies DIMM Mechanical Characteristics DIMM Type Information DIMM Attributes
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Internet Data Sheet
HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
HYS64T128020EDL-3S-C
HYS64T128020EDL-3-C
Organization
1 GByte x64 2 Ranks (x16)
2 GByte x64
HYS64T256020EDL-3-C
Product Type
1 GByte x64
2 GByte x64 2 Ranks (x8) PC2- 5300S-555 Rev. 1.2 HEX 07 3D 50 50 60 3C 1E 3C 2D 01 20 27 10 17 3C 1E 1E 00 06 3C 7F 80 18 22
2 Ranks (x8) 2 Ranks (x16) PC2- 5300S-444 Rev. 1.2 HEX 07 30 45 50 60 30 1E 30 2D 01 20 27 10 17 3C 1E 1E 00 06 39 7F 80 18 22 PC2- 5300S-555 Rev. 1.2 HEX 07 3D 50 50 60 3C 28 3C 2D 80 20 27 10 17 3C 1E 1E 00 06 3C 7F 80 18 22
Label Code JEDEC SPD Revision Byte# 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 Description Component Attributes
PC2- 5300S-444 Rev. 1.2 HEX 07 30 45 50 60 30 28 30 2D 80 20 27 10 17 3C 1E 1E 00 06 39 7F 80 18 22
tCK @ CLMAX -1 (Byte 18) [ns] tAC SDRAM @ CLMAX -1 [ns] tCK @ CLMAX -2 (Byte 18) [ns] tAC SDRAM @ CLMAX -2 [ns] tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns] tRAS.MIN [ns]
Module Density per Rank
tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns]
Analysis Characteristics
tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns]
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HYS64T256020EDL-3S-C
Internet Data Sheet
HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
HYS64T128020EDL-3S-C
HYS64T128020EDL-3-C
Organization
1 GByte x64 2 Ranks (x16)
2 GByte x64
HYS64T256020EDL-3-C
Product Type
1 GByte x64
2 GByte x64 2 Ranks (x8) PC2- 5300S-555 Rev. 1.2 HEX 00 51 60 47 39 3D 28 31 24 3E 22 23 00 00 00 00 12 87 7F 7F 7F 7F 7F 51
2 Ranks (x8) 2 Ranks (x16) PC2- 5300S-444 Rev. 1.2 HEX 00 51 60 47 39 3D 28 31 24 3E 22 24 00 00 00 00 12 55 7F 7F 7F 7F 7F 51 PC2- 5300S-555 Rev. 1.2 HEX 00 53 58 4F 34 38 24 37 32 44 1F 29 00 00 00 00 12 28 7F 7F 7F 7F 7F 51
Label Code JEDEC SPD Revision Byte# 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 Description PLL Relock Time
PC2- 5300S-444 Rev. 1.2 HEX 00 53 58 4F 34 38 24 37 32 44 1F 29 00 00 00 00 12 F5 7F 7F 7F 7F 7F 51
TCASE.MAX Delta / T4R4W Delta
Psi(T-A) DRAM T0 (DT0) T2N (DT2N, UDIMM) or T2Q (DT2Q, RDIMM) T2P (DT2P) T3N (DT3N) T3P.fast (DT3P fast) T3P.slow (DT3P slow) T4R (DT4R) / T4R4W Sign (DT4R4W) T5B (DT5B) T7 (DT7) Psi(ca) PLL Psi(ca) REG TPLL (DTPLL) TREG (DTREG) / Toggle Rate SPD Revision Checksum of Bytes 0-62 Manufacturer's JEDEC ID Code (1) Manufacturer's JEDEC ID Code (2) Manufacturer's JEDEC ID Code (3) Manufacturer's JEDEC ID Code (4) Manufacturer's JEDEC ID Code (5) Manufacturer's JEDEC ID Code (6)
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HYS64T256020EDL-3S-C
Internet Data Sheet
HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
HYS64T128020EDL-3S-C
HYS64T128020EDL-3-C
Organization
1 GByte x64 2 Ranks (x16)
2 GByte x64
HYS64T256020EDL-3-C
Product Type
1 GByte x64
2 GByte x64 2 Ranks (x8) PC2- 5300S-555 Rev. 1.2 HEX 00 00 xx 36 34 54 32 35 36 30 32 30 45 44 4C 33 53 43 20 20 20 1x xx xx
2 Ranks (x8) 2 Ranks (x16) PC2- 5300S-444 Rev. 1.2 HEX 00 00 xx 36 34 54 32 35 36 30 32 30 45 44 4C 33 43 20 20 20 20 1x xx xx PC2- 5300S-555 Rev. 1.2 HEX 00 00 xx 36 34 54 31 32 38 30 32 30 45 44 4C 33 53 43 20 20 20 1x xx xx
Label Code JEDEC SPD Revision Byte# 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 Description Manufacturer's JEDEC ID Code (7) Manufacturer's JEDEC ID Code (8) Module Manufacturer Location Product Type, Char 1 Product Type, Char 2 Product Type, Char 3 Product Type, Char 4 Product Type, Char 5 Product Type, Char 6 Product Type, Char 7 Product Type, Char 8 Product Type, Char 9 Product Type, Char 10 Product Type, Char 11 Product Type, Char 12 Product Type, Char 13 Product Type, Char 14 Product Type, Char 15 Product Type, Char 16 Product Type, Char 17 Product Type, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year
PC2- 5300S-444 Rev. 1.2 HEX 00 00 xx 36 34 54 31 32 38 30 32 30 45 44 4C 33 43 20 20 20 20 1x xx xx
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HYS64T256020EDL-3S-C
Internet Data Sheet
HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
HYS64T128020EDL-3S-C
HYS64T128020EDL-3-C
Organization
1 GByte x64 2 Ranks (x16)
2 GByte x64
HYS64T256020EDL-3-C
Product Type
1 GByte x64
2 GByte x64 2 Ranks (x8) PC2- 5300S-555 Rev. 1.2 HEX xx xx 00 FF
2 Ranks (x8) 2 Ranks (x16) PC2- 5300S-444 Rev. 1.2 HEX xx xx 00 FF PC2- 5300S-555 Rev. 1.2 HEX xx xx 00 FF
Label Code JEDEC SPD Revision Byte# 94 95 - 98 128 255 Description Module Manufacturing Date Week Module Serial Number Blank for customer use
PC2- 5300S-444 Rev. 1.2 HEX xx xx 00 FF
99 - 127 Not used
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HYS64T256020EDL-3S-C
Internet Data Sheet
HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
TABLE 26
SPD codes for PC2-4200
Product Type Organization HYS64T128020EDL-3.7-C HYS64T256020EDL-3.7-C 1 GByte x64 2 Ranks (x16) Label Code JEDEC SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Description Programmed SPD Bytes in EEPROM Total number of Bytes in EEPROM Memory Type (DDR2) Number of Row Addresses Number of Column Addresses DIMM Rank and Stacking Information Data Width Not used Interface Voltage Level PC2-4200S-444 Rev. 1.2 HEX 80 08 08 0D 0A 61 40 00 05 3D 50 00 82 10 00 00 0C 08 38 01 04 00 07 3D 50 50 60 3C 28 3C 2 GByte x64 2 Ranks (x8) PC2-4200S-444 Rev. 1.2 HEX 80 08 08 0E 0A 61 40 00 05 3D 50 00 82 08 00 00 0C 08 38 01 04 00 07 3D 50 50 60 3C 1E 3C
tCK @ CLMAX (Byte 18) [ns] tAC SDRAM @ CLMAX (Byte 18) [ns]
Error Correction Support (non-ECC, ECC) Refresh Rate and Type Primary SDRAM Width Error Checking SDRAM Width Not used Burst Length Supported Number of Banks on SDRAM Device Supported CAS Latencies DIMM Mechanical Characteristics DIMM Type Information DIMM Attributes Component Attributes
tCK @ CLMAX -1 (Byte 18) [ns] tAC SDRAM @ CLMAX -1 [ns] tCK @ CLMAX -2 (Byte 18) [ns] tAC SDRAM @ CLMAX -2 [ns] tRP.MIN [ns] tRRD.MIN [ns] tRCD.MIN [ns]
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Internet Data Sheet
HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
Product Type Organization
HYS64T128020EDL-3.7-C HYS64T256020EDL-3.7-C 1 GByte x64 2 Ranks (x16) 2 GByte x64 2 Ranks (x8) PC2-4200S-444 Rev. 1.2 HEX 2D 01 25 37 10 22 3C 1E 1E 00 06 3C 7F 80 1E 28 00 51 60 3F 32 3D 23 2C 24 36 22 24 00 00 00 00 12
Label Code JEDEC SPD Revision Byte# 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 Description
PC2-4200S-444 Rev. 1.2 HEX 2D 80 25 37 10 22 3C 1E 1E 00 06 3C 7F 80 1E 28 00 53 58 47 2E 38 20 32 32 3C 1F 27 00 00 00 00 12
tRAS.MIN [ns]
Module Density per Rank
tAS.MIN and tCS.MIN [ns] tAH.MIN and tCH.MIN [ns] tDS.MIN [ns] tDH.MIN [ns] tWR.MIN [ns] tWTR.MIN [ns] tRTP.MIN [ns]
Analysis Characteristics
tRC and tRFC Extension tRC.MIN [ns] tRFC.MIN [ns] tCK.MAX [ns] tDQSQ.MAX [ns] tQHS.MAX [ns]
PLL Relock Time
TCASE.MAX Delta / T4R4W Delta
Psi(T-A) DRAM T0 (DT0) T2N (DT2N, UDIMM) or T2Q (DT2Q, RDIMM) T2P (DT2P) T3N (DT3N) T3P.fast (DT3P fast) T3P.slow (DT3P slow) T4R (DT4R) / T4R4W Sign (DT4R4W) T5B (DT5B) T7 (DT7) Psi(ca) PLL Psi(ca) REG TPLL (DTPLL) TREG (DTREG) / Toggle Rate SPD Revision
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Internet Data Sheet
HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
Product Type Organization
HYS64T128020EDL-3.7-C HYS64T256020EDL-3.7-C 1 GByte x64 2 Ranks (x16) 2 GByte x64 2 Ranks (x8) PC2-4200S-444 Rev. 1.2 HEX AB 7F 7F 7F 7F 7F 51 00 00 xx 36 34 54 32 35 36 30 32 30 45 44 4C 33 2E 37 43 20 20 1x xx xx xx xx
Label Code JEDEC SPD Revision Byte# 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 - 98 Description Checksum of Bytes 0-62 Manufacturer's JEDEC ID Code (1) Manufacturer's JEDEC ID Code (2) Manufacturer's JEDEC ID Code (3) Manufacturer's JEDEC ID Code (4) Manufacturer's JEDEC ID Code (5) Manufacturer's JEDEC ID Code (6) Manufacturer's JEDEC ID Code (7) Manufacturer's JEDEC ID Code (8) Module Manufacturer Location Product Type, Char 1 Product Type, Char 2 Product Type, Char 3 Product Type, Char 4 Product Type, Char 5 Product Type, Char 6 Product Type, Char 7 Product Type, Char 8 Product Type, Char 9 Product Type, Char 10 Product Type, Char 11 Product Type, Char 12 Product Type, Char 13 Product Type, Char 14 Product Type, Char 15 Product Type, Char 16 Product Type, Char 17 Product Type, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number
PC2-4200S-444 Rev. 1.2 HEX 4B 7F 7F 7F 7F 7F 51 00 00 xx 36 34 54 31 32 38 30 32 30 45 44 4C 33 2E 37 43 20 20 1x xx xx xx xx
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Internet Data Sheet
HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
Product Type Organization
HYS64T128020EDL-3.7-C HYS64T256020EDL-3.7-C 1 GByte x64 2 Ranks (x16) 2 GByte x64 2 Ranks (x8) PC2-4200S-444 Rev. 1.2 HEX 00 FF
Label Code JEDEC SPD Revision Byte# 128 255 Description Blank for customer use
PC2-4200S-444 Rev. 1.2 HEX 00 FF
99 - 127 Not used
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Internet Data Sheet
HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
5
Package Outlines
FIGURE 5
Package Outline Raw Card A L-DIM-200-31
Notes 1. Thermal Sensor (Optional) 2. SPD or Combidevice (if used then no Thermal Sensor needed)
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Internet Data Sheet
HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
FIGURE 6
Package Outline Raw Card F - L-DIM-200-34
Notes 1. SPD or Combidevice (if used then no Thermal Sensor needed). 2. Thermal Sensor (Optional)
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Internet Data Sheet
HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
6
Product Type Nomenclature
field number. The detailed field description together with possible values and coding explanation is listed for modules in Table 28 and for components in Table 29.
Qimonda's nomenclature uses simple coding combined with some proprietary coding. Table 27 provides examples for module and component product type number as well as the
TABLE 27
Nomenclature Fields and Examples
Example for Field Number 1 Micro-DIMM DDR2 DRAM HYS HYB 2 64 18 3 T T 4 64/128 5 0 6 2 7 0 0 8 K A 9 M C 10 -5 -5 11 -A --
512/1G 16
TABLE 28
DDR2 DIMM Nomenclature
Field 1 2 3 4 Description Qimonda Module Prefix Module Data Width [bit] DRAM Technology Memory Density per I/O [Mbit]; Module Density1) Values HYS 64 72 T 32 64 128 256 512 5 6 7 8 9 Raw Card Generation Number of Module Ranks Product Variations Package, Lead-Free Status Module Type 0 .. 9 0, 2, 4 0 .. 9 A .. Z D M R U F Coding Constant Non-ECC ECC DDR2 256 MByte 512 MByte 1 GByte 2 GByte 4 GByte Look up table 1, 2, 4 Look up table Look up table SO-DIMM Micro-DIMM Registered Unbuffered Fully Buffered
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Internet Data Sheet
HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
Field 10
Description Speed Grade
Values -2.5F -2.5 -3 -3S -3.7 -5
Coding PC2-6400 5-5-5 PC2-6400 6-6-6 PC2-5300 4-4-4 PC2-5300 5-5-5 PC2-4200 4-4-4 PC2-3200 3-3-3 First Second
11
Die Revision
-A -B
1) Multiplying "Memory Density per I/O" with "Module Data Width" and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall module memory density in MBytes as listed in column "Coding".
TABLE 29
DDR2 DRAM Nomenclature
Field 1 2 3 4 Description Qimonda Component Prefix Interface Voltage [V] DRAM Technology Component Density [Mbit] Values HYB 18 T 256 512 1G 2G 5+6 Number of I/Os 40 80 16 7 8 9 10 Product Variations Die Revision Package, Lead-Free Status Speed Grade 0 .. 9 A B C F -25F -2.5 -3 -3S -3.7 -5 Coding Constant SSTL_18 DDR2 256 Mbit 512 Mbit 1 Gbit 2 Gbit x4 x8 x16 Look up table First Second FBGA, lead-containing FBGA, lead-free DDR2-800 5-5-5 DDR2-800 6-6-6 DDR2-667 4-4-4 DDR2-667 5-5-5 DDR2-533 4-4-4 DDR2-400 3-3-3
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Internet Data Sheet
HYS64T[128/256]020EDL-[25F/2.5/3/3S/3.7]-C SO-DIMM DDR2 SDRAM Module
Table of Contents
1 1.1 1.2 2 3 3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.4 4 5 6 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Speed Grade Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13 14 15 15 17 26 28
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Product Type Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
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Internet Data Sheet
Edition 2007-03 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 Munchen, Germany (c) Qimonda AG 2006. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. www.qimonda.com

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